Chip package and fabrication method thereof

ABSTRACT

A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.61/265,708, filed on Dec. 1, 2009, the entirety of which is incorporatedby reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a chip package, and in particularrelates to a chip package which can protect conductive pads from damageduring a cutting process and a redistribution stack layer and afabrication method thereof.

2. Description of the Related Art

Wafer level packaging technology has been developed for packaging chips.After a wafer level package is completed, a cutting process is performedbetween chips to separate the chips from each other.

However, when using a cutter to form an opening between the chips in thecutting process, a lot of chipping is produced. The chippings damage andscratch bonding pads of the chip during the cutting process, such thatthe reliability of wire bonding of the chip package is reduced followingsubsequent processes and the electrical property of the conventionalchip package is poor.

Thus, a chip package which can mitigate the above mentioned problems andprevent the conductive pads of chips from damage during a cuttingprocess is desired.

BRIEF SUMMARY OF THE INVENTION

According to an illustrative embodiment, a chip package is provided. Thechip package comprises a semiconductor substrate containing a chip,having a device area and a peripheral bonding pad area. A plurality ofconductive pads is disposed at the peripheral bonding pad area. A chippassivation layer is disposed over the semiconductor substrate, exposingthe conductive pads. An insulating protective layer is disposed over thedevice area and a packaging layer is disposed over the insulatingprotective layer, exposing the conductive pads.

According to another illustrative embodiment, a method for fabricating achip package is provided. The method comprises providing a semiconductorwafer containing a plurality of device areas and a peripheral bondingpad area disposed between any two adjacent device areas, wherein theperipheral bonding pad area includes a plurality of conductive pads, anda chip passivation layer covering the semiconductor wafer, exposing theconductive pads. An insulating protective layer is formed on the chippassivation layer, covering the conductive pads. A packaging layer isprovided and the semiconductor wafer is bonded to the packaging layer.The packaging layer is patterned to form a plurality of openings toexpose the insulating protective layer at the peripheral bonding padarea. Then, the insulating protective layer at the peripheral bondingpad area is removed to expose the conductive pads by using the packaginglayer as a hard mask.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIGS. 1A-1F are illustrative cross sections showing the steps forfabricating a chip package according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of a mode for carrying out the invention.This description is made for the purpose of illustrating the generalprinciples of the invention and should not be taken in a limiting sense.The scope of the invention is best determined by reference to theappended claims. Wherever possible, the same reference numbers are usedin the drawings and the descriptions to refer the same or like parts. Inthe drawings, the size of some of the elements may be exaggerated andnot drawn to scale for illustrative purposes. The dimensions and therelative dimensions do not correspond to actual dimensions to practiceof the invention. Further, parts of the elements in the drawings areillustrated by the following description. Some elements not shown in thedrawings are known by one skilled the art.

The embodiments of chip packages of the invention and fabricationmethods thereof are illustrated by embodiments of fabricating imagesensor packages in the following description. However, it should beappreciated that the invention may also be applied to forming othersemiconductor chip packages. Therefore, the packages of the embodimentsof the invention may be applied to active or passive devices, orelectronic components with digital or analog circuits, such asoptoelectronic devices, micro electro mechanical systems (MEMS), microfluidic systems, and physical sensors for detecting heat, light, orpressure. Particularly, a wafer scale package (WSP) process may beapplied to package semiconductor chips, such as image sensors, solarcells, RF circuits, accelerators, gyroscopes, micro actuators, surfaceacoustic wave devices, pressure sensors, and ink printer heads.

The wafer level packaging process herein mainly means that after thepackaging process is accomplished during a wafer stage, a wafer withchips is cut to obtain separate independent packages. However, in anembodiment of the invention, separate independent chips may beredistributed overlying a supporting wafer and then be packaged, whichmay also be referred to as a wafer level packaging process. In addition,the wafer level packaging process may also be adapted to form chippackages of multi-layered integrated circuit devices by stacking aplurality of wafers having integrated circuits together.

An embodiment of the invention provides a chip packages and afabrication method thereof. After a wafer level package of the abovementioned devices is completed and the devices are separated from eachother to form separate independent chip packages by a cutting process,the conductive pads of the chip packages are protected to prevent fromdamage by residues produced from the cutting process, or scratching theconductive pads.

Referring to FIGS. 1A-1F, cross sections illustrating the steps forfabricating a chip package according to an embodiment of the inventionare shown. As shown in FIG. 1A, first, a semiconductor wafer 100containing a plurality of chips is provided. The semiconductor substrate100 has a plurality of device areas 100A and a peripheral bonding padarea 100B disposed between any two adjacent device areas 100A. Aplurality of conductive pads 104 is disposed at the peripheral bondingpad area 100B. Moreover, in general, the semiconductor wafer 100 iscovered with a chip passivation layer 106 when it is produced from asemiconductor wafer factory. The chip passivation layer 106 may be asilicon nitride layer. Meanwhile, in order to electrically connect thedevices of the chip to external circuits, the chip passivation layer 106is defined by the semiconductor wafer factory to form a plurality ofopenings beforehand to expose conductive pads 104 therein.

Next, referring to FIG. 1B, an insulating protective layer 108 is formedon the overall surface of the semiconductor wafer 100 to cover the chippassivation layer 106 and the conductive pads 104. The material of theinsulating protective layer 108 is different from the material of thechip passivation layer 106. The insulating protective layer 108 may be asilicon oxide layer formed by a chemical vapor deposition method.

Then, referring to FIG. 1C, a packaging layer 200 is provided to bondwith the semiconductor wafer 100. The packaging layer 200 may be a glasssubstrate or another blank silicon wafer. In an embodiment, thepackaging layer 200 is separated from the semiconductor wafer 100 by aspacer 110 and thereby a cavity 116 surrounded by the spacer 110 isformed. The spacer 100 may be a sealant or a photosensitive insulatingmaterial, such as epoxy resin, solder mask materials, etc. Moreover, thespacer 100 may be firstly formed on the insulating protective layer 108and then bonded to the packaging layer 200 through an adhesive layer(not shown). On the other hand, the spacer 100 may be firstly formed onthe packaging layer 200 and then bonded to the insulating protectivelayer 108 through an adhesive layer (not shown).

Referring to FIG. 1D, in a cutting process, a cutter knife (not shown)is used to form openings 114 in the packaging layer 200 to expose thesurface of the peripheral bonding pad area 100B. Meanwhile, chipping118, formed from the cutting process, for example glass or silicon waferchipping, fall down onto the insulating protective layer 108. Becausethe conductive pads 104 are covered with the insulating protective layer108, the conductive pads 104 are prevented from damage or scratching bythe chipping 118 during the cutting process.

Next, referring to FIG. 1E, at least a portion of the insulatingprotective layer 108 at the peripheral bonding pad area 100B is removedthrough the openings 114 of the packaging layer 200. Thus, theconductive pads 104 and the chip passivation layer 106 are exposed tosubsequently form electrical connections between the conductive pads 104and external circuits. Meanwhile, the residual insulating protectivelayer 108 covers all of the device area 100A surrounded by the spacer110. In the embodiment, the insulating protective layer 108 may be anon-photosensitive insulating material, such as silicon oxides.Accordingly, the packaging layer 200 having the openings 114 can be usedas a hard mask, and the insulating protective layer 108 at theperipheral bonding pad area 100B can be removed by an etching process.Therefore, there is no need to use an extra photolithography process toform a patterned photoresist as a mask in the embodiment of theinvention. Moreover, the material of the insulating protective layer 108is different from the material of the chip passivation layer 106, suchthat the chip passivation layer 106 can be used as an etch stop layerfor the insulating protective layer 108. In another embodiment, theinsulating protective layer 108 at the peripheral bonding pad area 100Bcan be defined by a photolithography process to form openings to exposethe conductive pads 104.

In addition, the insulating protective layer 108 can be selected from aphotosensitive material and an exposure process is performed to theinsulating protective layer 108. Then, a development process isperformed to remove the insulating protective layer 108 at theperipheral bonding pad area 100B through the openings 114 of thepackaging layer 200. In the embodiment, the material of the spacer 100is an opaque material. A portion of the insulating protective layer 108a disposed under the spacer 110 is not exposed or an exposure extentthereof is smaller than other portions of the insulating protectivelayer, such that the portion of insulating protective layer 108 adisposed under the spacer 110 has hardness which is greater than thehardness of other portions of the insulating protective layer 108 a; forexample the portions of the insulating protective layer 108 a disposedunder the cavity 116, which is exposed but not developed. Therefore, themechanical strength of the structure below the spacer 110 is enhanced.

Moreover, because the adhesion between the spacer 110 and the materialof silicon oxides is greater than the adhesion between the spacer 110and the material of silicon nitrides, in the embodiments of theinvention, the interface adhesion between the spacer 110 and the chippassivation layer 106 made of silicon nitrides is less than theinterface adhesion between the spacer 110 and the insulating protectivelayer 108 a made of silicon oxides. Thus, the extra insulatingprotective layer 108 a formed from silicon oxide can improve reliabilityof chip packages.

Next, referring to FIGS. 1E and 1F, the semiconductor wafer 100 isdivided along a scribe line 112 at the peripheral bonding pad area 100Bto form a plurality of separated independent chip packages as shown inFIG. 1F.

Referring to FIG. 1F, a cross section of a chip package according to anembodiment of the invention is shown. The semiconductor wafer is dividedalong the scribe line 112 to form the chip packages 102. Thesemiconductor substrate 100 of the chip package 102 is, for exampleformed from dicing the semiconductor wafer containing the chips. Thesemiconductor substrate 100 can be divided into the device area 100A andthe peripheral bonding pad area 100B, wherein the device area 100A issurrounded by the peripheral bonding pad area 100B.

The peripheral bonding pad area 100B of the semiconductor substrate 100has a plurality of conductive pads 104 thereon. The conductive pad 104is, for example a bonding pad, which is electrically connected to theinner portion of the chip through metal interconnects (not shown). Thesurface of the semiconductor substrate 100 is covered with the chippassivation layer 106; for example a layer made of silicon nitrides orsilicon oxynitrides. The conductive pads 104 are exposed by the chippassivation layer 106 and can be electrically connected to an externalcircuit by a wire bonding method. The chip passivation layer 106disposed at the device area 100A is covered with the insulatingprotective layer 108 a; for example a layer made of silicon oxides. Inaddition, the packaging layer 200 is further disposed on the insulatingprotective layer 108 a.

In an embodiment, the chip packages can be applied to, but are notlimited to, image sensor devices, such as complementary metal oxidesemiconductor (CMOS) devices or charge-couple devices (CCD). Moreover,the chip packages can also be applied to micro electro mechanical system(MEMS) devices.

It is preferable that the conductive pads 104 are formed from copper(Cu), aluminum (Al) or other suitable metal materials. The spacer 110can be disposed between the packaging layer 200 and the semiconductorsubstrate 100 to form the cavity 116 between the packaging layer 200 andthe semiconductor substrate 100, wherein the cavity 116 is surrounded bythe spacer 110.

In an embodiment, the packaging layer 200 may be a transparent substratemade of glass, quartz, opal, plastic or other materials permit lightpassing through. Moreover, a filter and/or an anti-reflective layer canbe selectively formed on the packaging layer 200. In the embodiments ofchip packages for non-photosensitive devices, the packaging layer 200can be a semiconductor layer, for example a silicon covering layer.

In another embodiment, the spacer 100 can completely fill between theinsulating protective layer 108 a and the packaging layer 200, such thatno cavity is formed between the insulating protective layer 108 a andthe packaging layer 200.

The spacer 110 can be made of epoxy resin, a solder mask or othersuitable insulating materials.

According to an embodiment of the invention, the insulating protectivelayer is formed on the conductive pads during the cutting process forwafer scale packages, thus the conductive pads can be prevented fromdamage and scratching by the chipping formed from the cutting process.Moreover, in the subsequent process for removing the insulatingprotective layer, the packaging layer with openings formed by thecutting process can be used as a hard mask, such that there is no needto form an extra patterned photoresist to serve as a mask.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. To the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A chip package, comprising: a semiconductor substrate, having adevice area and a peripheral bonding pad area, wherein the peripheralbonding pad area surrounds the device area; a plurality of conductivepads disposed at the peripheral bonding pad area of the semiconductorsubstrate; a chip passivation layer disposed over the semiconductorsubstrate and exposing the conductive pads; an insulating protectivelayer disposed over the device area; and a packaging layer disposed onthe insulating protective layer and exposing the conductive pads.
 2. Thechip package as claimed in claim 1, wherein the insulating protectivelayer covers the device area, not reaching to the peripheral bonding padarea, and the conductive pads and the chip passivation layer at theperipheral bonding pad area are exposed by the packaging layer.
 3. Thechip package as claimed in claim 1, further comprising a spacer disposedbetween the packaging layer and the insulating protective layer.
 4. Thechip package as claimed in claim 1, further comprising a cavity formedbetween the packaging layer and the insulating protective layer, whereinthe cavity is surrounded by the spacer.
 5. The chip device package asclaimed in claim 1, wherein the material of the insulating protectivelayer is different from the material of the chip passivation layer. 6.The chip device package as claimed in claim 5, wherein the material ofthe chip passivation layer comprises silicon nitride and the material ofthe insulating protective layer comprises silicon oxide.
 7. The chippackage as claimed in claim 5, wherein the material of the insulatingprotective layer comprises a photosensitive insulating material.
 8. Thechip package as claimed in claim 4, wherein a portion of the insulatingprotective layer under the spacer has hardness which is greater thanthat of other portions of the insulating protective layer.
 9. The chippackage as claimed in claim 5, wherein the packaging layer comprises atransparent substrate or a semiconductor substrate.
 10. A method forfabricating a chip package, comprising: providing a semiconductor wafer,containing a plurality of device areas and a peripheral bonding pad areadisposed between any two adjacent device areas, wherein the peripheralbonding pad area includes a plurality of conductive pads, and a chippassivation layer covering the semiconductor wafer and exposing theconductive pads; forming an insulating protective layer on the chippassivation layer, covering the conductive pads; providing a packaginglayer; bonding the semiconductor wafer with the packaging layer;patterning the packaging layer to form a plurality of openings, exposingthe insulating protective layer at the peripheral bonding pad area; andusing the packaging layer as a hard mask to remove the insulatingprotective layer at the peripheral bonding pad area, exposing theconductive pads.
 11. The method as claimed in claim 10, wherein the stepof patterning the packaging layer comprises a cutting process andwherein during the cutting process, the conductive pads are covered withthe insulating protective layer.
 12. The method as claimed in claim 11,wherein the step of removing the insulating protective layer comprisesan etching process.
 13. The method as claimed in claim 10, wherein thematerial of the insulating protective layer is different from thematerial of the chip passivation layer.
 14. The method as claimed inclaim 13, wherein the material of the chip passivation layer comprisessilicon nitride and the material of the insulating protective layercomprises silicon oxide.
 15. The method as claimed in claim 10, whereinthe material of the insulating protective layer comprises aphotosensitive insulating material.
 16. The method as claimed in claim10, further comprising; forming a spacer between the packaging layer andthe insulating protective layer; and forming a cavity between thepackaging layer and the insulating protective layer, wherein the cavityis surrounded by the spacer.
 17. The method as claimed in claim 16,further comprising performing an exposure process to the photosensitiveinsulating material, wherein a portion of the photosensitive insulatingmaterial disposed under the spacer are exposed to an exposure extentsmaller than that of other portions of the photosensitive insulatingmaterial.
 18. The method as claimed in claim 17, wherein the portion ofthe insulating protective layer disposed under the spacer has hardnesswhich is greater than that of the other portions of the insulatingprotective layer.
 19. The method as claimed in claim 16, wherein thepackaging layer comprises a transparent substrate or a semiconductorsubstrate.